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CAT34C02 2 kb I2C EEPROM for DDR2 DIMM Serial Presence Detect
Description
The CAT34C02 is a 2 kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory) or by setting an internal Write Protect flag via Software command (this protects the lower half of the memory). In addition to Permanent Software Write Protection, the CAT34C02 also features JEDEC compatible Reversible Software Write Protection for DDR2 Serial Presence Detect (SPD) applications operating over the 1.7 V to 3.6 V supply voltage range. The CAT34C02 is fully backwards compatible with earlier DDR1 SPD applications operating over the 1.7 V to 5.5 V supply voltage range.
Features
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TSSOP-8 Y SUFFIX CASE 948AL
TDFN-8 VP2 SUFFIX CASE 511AK
UDFN-8 HU3 SUFFIX CASE 517AX
UDFN-8 EP HU4 SUFFIX CASE 517AZ
* * * * * * * * * * *
Supports Standard and Fast I2C Protocol 1.7 V to 5.5 V Supply Voltage Range 16-Byte Page Write Buffer Hardware Write Protection for Entire Memory Software Write Protection for Lower 128 Bytes Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Range This Device is Pb-Free, Halogen Free/BFR Free and RoHS Compliant*
VCC
PIN CONFIGURATION
A0 A1 A2 VSS 1 VCC WP SCL SDA
TSSOP (Y), TDFN (VP2), UDFN (HU3), UDFN (HU4) For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTION
Pin Name A0, A1, A2 Function Device Address Input Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground
SCL CAT34C02 SDA
SDA SCL
A2, A1, A0 WP
WP VCC VSS
Figure 1. Functional Symbol
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 14
1
Publication Order Number: CAT34C02/D
CAT34C02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Voltage on Pin A0 with Respect to Ground Rating -45 to +130 -65 to +150 -0.5 to +6.5 -0.5 to +10.5 Unit C C V V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol NEND (Note 3) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25C
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = -40C to +85C, unless otherwise specified.)
Symbol ICC ISB IL VIL VIH VOL Parameter Supply Current Test Conditions VCC < 3.6 V, fSCL = 100 kHz VCC > 3.6 V, fSCL = 400 kHz Standby Current I/O Pins at GND or VCC, VCC = 1.7 V I/O Pins at GND or VCC, VCC > 1.7 V I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage VCC > 2.5 V, IOL = 3 mA VCC < 2.5 V, IOL = 1 mA Pin at GND or VCC -0.5 0.7 x VCC Min Max 1 2 1 2 2 0.3 x VCC VCC + 0.5 0.4 0.2 mA V mA Units mA
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = -40C to +85C, unless otherwise specified.)
Symbol CIN (Note 4) IWP (Note 5) Parameter SDA I/O Pin Capacitance Other Input Pins WP Input Current VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.6 V VIN < VIH, VCC = 1.7 V VIN > VIH Conditions VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V Max 8 6 130 120 80 2 mA Units pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
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CAT34C02
Table 5. A.C. CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = -40C to +85C) (Note 6)
Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR (Note 7) tF (Note 7) tSU:STO tBUF tAA tDH Ti (Note 7) tSU:WP tHD:WP tWR tPU (Notes 7 & 8) 6. 7. 8. Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data Hold Time Data Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to SDA Data Out Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 4 4.7 3.5 100 100 4 4.7 4 4.7 0 250 1000 300 0.6 1.3 0.9 Parameter Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 Min Fast Max 400 Units kHz ms ms ms ms ms ns ns ns ms ms ms ns ns ms ms ms ms
Test conditions according to "A.C. Test Conditions" table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. THERMAL CHARACTERISTICS (Air velocity = 0 m/s, 4 layers PCB) (Notes 9 and 10)
Part Number CAT34C02Y CAT34C02VP2 CAT34C02HU3 CAT34C02HU4 Package TSSOP TDFN UDFN UDFN qJA 64 92 101 101 qJC 37 15 18 18 Units C/W C/W C/W C/W
9. TJ = TA + PD * qJA, where: TJ is the Junction Temperature, TA the Ambient Temperature, PD the Power dissipation. Example: CAT34C02VP2, VCC = 3.0 V, ICCmax = 1 mA, TA = 85C: TJ = 85C + 3 mW * 92C/W = 85.276C. 10. TJ = TC + PD * qJC, where: TC is the Case Temperature, etc.
Table 7. A.C. TEST CONDITIONS
Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 VCC to 0.8 VCC 50 ns 0.3 VCC, 0.7 VCC 0.5 VCC Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT34C02
Power-On Reset (POR) The CAT34C02 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The CAT34C02 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against `brown-out' failure following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on-chip pull-down resistor. Functional Description The CAT34C02 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT34C02 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. I2C Bus Protocol The I2C bus consists of two `wires', SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2).
Start
The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all receivers. Absent a START, a Slave will not respond to commands.
Stop
The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 5.
SDA
SCL START BIT STOP BIT
Figure 2. Start/Stop Timing
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CAT34C02
1 0 1 0 A2 A1 A0 R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACK DELAY ( tAA) ACK SETUP ( tSU:DAT)
Figure 4. Acknowledge Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
Figure 5. Bus Timing
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed by Slave address, byte address and data to be written (Figure 6). The Slave acknowledges all 3 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 7). During internal Write, the Slave will not acknowledge any Read or Write request from the Master.
Page Write
The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a `wrap-around' fashion (within the selected page). The internal Write cycle starts immediately following the STOP.
Acknowledge Polling
The CAT34C02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. A page is selected by the 4 most significant bits of the address byte following the Slave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 8).
Acknowledge polling can be used to determine if the CAT34C02 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a `Selective Read' command (see READ OPERATIONS). The CAT34C02 will not acknowledge the Slave address, as long as internal Write is in progress. Delivery State The CAT34C02 is shipped `unprotected', i.e. neither SWP flag is set. The entire 2 kb memory is erased, i.e. all bytes are FFh.
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CAT34C02
S T A R T S A C K A C K A C K S T O P P
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS
DATA
Figure 6. Byte Write Timing
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 7. Write Cycle Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+P
S T O P P
A C K
A C K
A C K
A C K
A C K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Figure 8. Page Write Timing
BYTE ADDRESS 1 SCL 8 9 1
DATA 8
SDA
A7
A0 tSU:WP
D7
D0
WP tHD:WP
Figure 9. WP Timing
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CAT34C02
Read Operations
Immediate Address Read
In standby mode, the CAT34C02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that `previous' byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT34C02 is presented with a Slave address containing a `1' in the R/W bit position (Figure 10), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition.
Selective Read
The address counter can be initialized by performing a `dummy' Write operation (Figure 11). Here the START is followed by the Slave address (with the R/W bit set to `0') and the desired byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the `Immediate Address Read' sequence, as described earlier.
Sequential Read
The Read operation can also be started at an address different from the one stored in the internal address counter.
S T A R T S
If the Master acknowledges the 1st data byte transmitted by the CAT34C02, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will `wrap-around' to the beginning of memory, etc. Sequential Read works with either `Immediate Address Read' or `Selective Read', the only difference being the starting byte address.
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
S T O P P A C K DATA N O A C K
SCL
8
9
SDA
8th Bit DATA OUT NO ACK STOP
Figure 10. Immediate Address Read Timing
S T A R T S A C K A C K S T A R T S A C K DATA n N O A C K S T O P P A C K A C K A C K A C K N O A C K S T O P P
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS (n)
SLAVE ADDRESS
Figure 11. Selective Read Timing
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
Figure 12. Sequential Read Timing
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CAT34C02
Software Write Protection The lower half of memory (first 128 bytes) can be protected against Write requests by setting one of two Software Write Protection (SWP) flags. The Permanent Software Write Protection (PSWP) flag can be set or read while all address pins are at regular CMOS levels (GND or VCC), whereas the very high voltage VHV must be present on address pin A0 to set, clear or read the Reversible Software Write Protection (RSWP) flag. The D.C. OPERATING CONDITIONS for RSWP operations are shown in Table 8. The SWP commands are listed in Table 9. All commands are preceded by a START and terminated with a STOP, following the ACK or NoACK from the CAT34C02. All SWP related Slave addresses use the pre-amble: 0110 (6h), instead of the regular 1010 (Ah) used for memory access. For PSWP commands, the three address pins can be at any logic level, whereas for RSWP commands the address pins must be at pre-assigned logic levels. VHV is interpreted as logic `1'. The VHV condition must be established on pin A0 before the START and maintained just beyond the STOP. Otherwise an RSWP request could be interpreted by the CAT34C02 as a PSWP request. The SWP Slave addresses follow the standard I2C convention, i.e. to read the state of the SWP flag, the LSB of the Slave address must be `1', and to set or clear a flag, it must be `0'. For Write commands a dummy byte address and dummy data byte must be provided (Figure 14). In contrast to a regular memory Read, a SWP Read does not return Data. Instead the CAT34C02 will respond with NoACK if the flag
Table 8. RSWP D.C. OPERATING CONDITIONS (Note 11)
Symbol DVHV IHVD VHV IHV Parameter A0 Overdrive (VHV - VCC) A0 High Voltage Detector Current A0 Very High Voltage A0 Input Current @ VHV 7 Test Conditions 1.7 V < VCC < 3.6 V Min 4.8 0.1 10 1 Max Units V mA V mA
is set and with ACK if the flag is not set. Therefore, the Master can immediately follow up with a STOP, as there is no meaningful data following the ACK interval (Figure 15). Hardware Write Protection With the WP pin held HIGH, the entire memory, as well as the SWP flags are protected against Write operations, see Memory Protection Map below. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT34C02. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT34C02 will not acknowledge the data byte and the Write request will be rejected.
FFH
Hardware Write Protectable (by connecting WP pin to VCC) 7FH Software Write Protectable (by setting the write protect flags) 00H
Figure 13. Memory Protection Map
11. To prevent damaging the CAT34C02 while applying VHV, it is strongly recommended to limit the power delivered to pin A0, by inserting a series resistor (> 1.5 kW) between the supply and the input pin. The resistance is only limited by the combination of VHV and maximum IHVD. While the resistor can be omitted if VHV is clamped well below 10 V, it nevertheless provides simple protection against EOS events. As an example: VCC = 1.7 V, VHV = 8 V, 1.5 kW < RS < 15 kW.
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CAT34C02
Table 9. SWP COMMANDS
Control Pin Levels (Note 12) WP X Set PSWP GND VCC X X X Set GND RSWP VCC X X Clear GND RSWP V CC X A2 A2 A2 A2 A2 GND GND GND GND GND GND GND GND GND A1 A1 A1 A1 A1 GND GND GND GND GND VCC VCC VCC VCC A0 A0 A0 A0 A0 VHV VHV VHV VHV VHV VHV VHV VHV VHV Flag State (Note 13) PSWP 1 0 0 0 1 0 0 0 0 1 0 0 0 Slave Address b3 A2 A2 A2 A2 0 0 0110 0 0 0 0 0 0 0 b2 A1 A1 A1 A1 0 0 0 0 0 1 1 1 1 b1 A0 A0 A0 A0 1 1 1 1 1 1 1 1 1 b0 X 0 0 1 X X 0 0 1 X 0 0 1 ACK ? No Yes Yes Yes No No Yes Yes Yes No Yes Yes Yes X X Yes Yes X X Yes No Yes No X X Yes Yes X X Yes No Yes No X X Yes Yes X X Yes No Yes No Address Byte ACK ? Data Byte ACK ? Write Cycle
Action
RSWP b7 to b4 X X X X X 1 0 0 0 X X X X
12. Here A2, A1 and A0 are either at VCC or GND. 13. 1 stands for `Set', 0 stands for `Not Set', X stands for `don't care'.
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS X XXXXXXX A C K X = Don't Care A C K
DATA XXXXX XXX
S T O P P
N A C or O K A C K
Figure 14. Software Write Protect (Write)
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
S T O P P
N A C or O K A C K
Figure 15. Software Write Protect (Read)
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CAT34C02
PACKAGE DIMENSIONS
TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O
b
SYMBOL
A A1 A2 b E1 E c D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 2.90 6.30 4.30
NOM
MAX
1.20 0.15
0.90
1.05 0.30 0.20
3.00 6.40 4.40 0.65 BSC 1.00 REF
3.10 6.50 4.50
0.50
0.60
0.75
e
0
8
TOP VIEW D
A2
A
q1
c
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
L1 END VIEW
L
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CAT34C02
PACKAGE DIMENSIONS
TDFN8, 2x3 CASE 511AK-01 ISSUE A
D A e b
E
E2 PIN#1 IDENTIFICATION
A1 PIN#1 INDEX AREA D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 FRONT VIEW A2 A3
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
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CAT34C02
PACKAGE DIMENSIONS
UDFN8, 2x3 CASE 517AX-01 ISSUE O
D A DETAIL A
DAP SIZE 1.3 x 1.8
E PIN #1 IDENTIFICATION
E2
A1 PIN #1 INDEX AREA TOP VIEW SIDE VIEW D2 BOTTOM VIEW
SYMBOL A A1 A3 b D D2 E E2 e K L
MIN 0.45 0.00 0.20 1.90 1.50 2.90 0.10
NOM 0.50 0.02 0.127 REF 0.25 2.00 1.60 3.00 0.20 0.50 TYP 0.10 REF
MAX 0.55 0.05 K 0.30 2.10 1.70 3.10 0.30 e
b
L
DETAIL A
A3 0.40 A
0.30
0.35
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
A1 FRONT VIEW
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CAT34C02
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD CASE 517AZ-01 ISSUE O
D
A
b
e L
DAP SIZE 1.8 x 1.8 E2
E
PIN #1 IDENTIFICATION
A1 PIN #1 INDEX AREA TOP VIEW SIDE VIEW D2 BOTTOM VIEW
SYMBOL A A1 A3 b D D2 E E2 e L
MIN 0.45 0.00 0.20 1.95 1.35 2.95 1.25 0.25
NOM 0.50 0.02 0.127 REF 0.25 2.00 1.40 3.00 1.30 0.50 REF 0.30
MAX 0.55 0.05 0.30 2.05 1.45 3.05 1.35 0.35 A3 0.0 - 0.05 DETAIL A 0.065 REF Copper Exposed 0.065 REF DETAIL A FRONT VIEW A3 A
Notes: (1) All dimensions are in millimeters. (2) Refer JEDEC MO-236/MO-252.
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CAT34C02
Example of Ordering Information CAT34C02 MATURE PRODUCT (Note 16)
Prefix CAT Device # 34C02 Suffix Y I -G T5
Company ID Product Number 34C02 Package Y: TSSOP VP2: TDFN HU3: UDFN HU4: UDFN
Temperature Range I = Industrial (-40C to +85C)
Lead Finish G: NiPdAu Lead Plating
Tape & Reel (Note 22) T: Tape & Reel 4: 4000/Reel (Note 17) 5: 5000/Reel (Note 18)
CAT34C02 NEW PRODUCT (Note 19)
Prefix CAT Device # 34C02 Suffix Y I -G T5 A
Company ID Product Number 34C02
Temperature Range I = Industrial (-40C to +85C)
Tape & Reel (Note 22) T: Tape & Reel 4: 4000/Reel (Note 17) 5: 5000/Reel (Note 18)
Die Identifier
Package Y: TSSOP VP2: TDFN (Note 20) HU3: UDFN (Note 20) HU4: UDFN (Note 20)
Lead Finish G: NiPdAu Lead Plating
14. All packages are RoHS-compliant (Lead-free, Halogen-free) 15. The standard lead finish is NiPdAu. 16. The device used in the above example is a CAT34C02YI-GT5 mature product (TSSOP, Industrial Temperature, NiPdAu, 5000 pcs / Reel) 17. The TDFN and UDFN packages are available in 4000 pcs/Reel (i.e., CAT34C02VP2I-GT4, CAT34C02HU3I-GT4, CAT34C02HU4I-GT4). 18. The TSSOP (Y) package (i.e., CAT34C02YI-GT5) is available in 5000 pcs / Reel. 19. The CAT34C02 new product orderable part number requires the letter "A" added at the end of the OPN. 20. For the TDFN (VP2) and UDFN (HU3, HU4) packages of CAT34C02 new product, there is NO hyphen in the orderable part number (example: CAT34C02VP2IGT4A) 21. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 22. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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CAT34C02
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
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CAT34C02/D

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Price & Availability of CAT34C02

	To Download CAT34C02 Datasheet File
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